/* Copyright (c) 2025 Beijing Semidrive Technology Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 * http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */

/**
 * @file Eth_PBCfg.h
 * @brief AutoSAR ETH configuration header file
 * @details Automatically generated by user settings
 * @date 2025-03-25 19:03:22
 */


#ifndef ETH_PBCFG_H_
#define ETH_PBCFG_H_

#include "Eth_GeneralTypes.h"
#include "Eth_Portable.h"

#ifdef __cplusplus
extern "C"{
#endif
/* Version and Check Begin */
/* Version Info Begin */
#define ETH_CFG_H_VENDOR_ID    0x8C
#define ETH_CFG_H_MODULE_ID    88
#define ETH_CFG_H_AR_RELEASE_MAJOR_VERSION    4
#define ETH_CFG_H_AR_RELEASE_MINOR_VERSION    3
#define ETH_CFG_H_AR_RELEASE_REVISION_VERSION 1
#define ETH_CFG_H_SW_MAJOR_VERSION    1
#define ETH_CFG_H_SW_MINOR_VERSION    0
#define ETH_CFG_H_SW_PATCH_VERSION    0
#define ETH_MODULE_ID   88

#ifndef ETH_MAC_LAYER_SPEED_100M
#define  ETH_MAC_LAYER_SPEED_100M  0u
#endif

#ifndef ETH_MAC_LAYER_SPEED_10G
#define  ETH_MAC_LAYER_SPEED_10G 1u
#endif

#ifndef ETH_MAC_LAYER_SPEED_10M
#define  ETH_MAC_LAYER_SPEED_10M 2u
#endif

#ifndef ETH_MAC_LAYER_SPEED_1G
#define  ETH_MAC_LAYER_SPEED_1G 3u
#endif

#ifndef LIGHT
#define LIGHT 0u
#endif

#ifndef REDUCED
#define REDUCED 1u
#endif

#ifndef SERIAL
#define SERIAL 2u
#endif

#ifndef STANDARD
#define STANDARD 3u
#endif

#ifndef UNIVERSAL_SERIAL
#define UNIVERSAL_SERIAL 4u
#endif

/* MAC layer interface (data) bandwith class 1Gbit/s (e.g. GMII, RGMII, SGMII, RvGMII, USGMII)*/
#ifndef ETH_MAC_LAYER_TYPE_XGMII
#define ETH_MAC_LAYER_TYPE_XGMII 0u
#endif
/* MAC layer interface (data) bandwith class 100Mbit/s (e.g. RMII, RvMII, SMII, RvMII) */
#ifndef ETH_MAC_LAYER_TYPE_XMII
#define ETH_MAC_LAYER_TYPE_XMII 1u
#endif
/* MAC layer interface (data) bandwith class 10Gbit/s */
#ifndef ETH_MAC_LAYER_TYPE_XXGMII
#define ETH_MAC_LAYER_TYPE_XXGMII 2u
#endif
/**
* @brief
*/
#define ETH_DEV_ERROR_DETECT (STD_ON)
/**
* @brief
*/
#define MDIO_DET_CHECK_BYPASS (STD_OFF)
/**
* @brief
*/
#define ETH_UPDATE_FILTER_API (STD_ON)
/**
* @brief
*/
#define CHECKSUM_INSERTION_CONFIG TDES3_CKSUM_INS_DISABLE
/**
* @brief
*/
#define ETH_GET_COUNTVAL_API (STD_ON)
/**
* @brief
*/
#define ETH_GET_RXSTATS_API (STD_ON)
/**
* @brief
*/
#define ETH_GET_TXSTATS_API (STD_ON)
/**
* @brief
*/
#define ETH_GET_TXERRORCOUNT_API (STD_ON)
/**
* @brief
*/
#define ETH_GET_GLOBALTIME_API (STD_ON)
/**
* @brief
*/
#define ETH_GET_VERSION_INFO_API (STD_OFF)
/**
* @brief
*/
#define ETH_CTRL_MII_ENABLE_API (STD_ON)
/**
* @brief
*/
#define ETH_DRIVER_INSTANCE (0U)
/**
* @brief
*/
#define ETH_MAXCTRLS_SUPPORTED (1U)
/**
* @brief
*/
#define ETH_MAX_DMA_CHANNEL (3U)

/**
* @brief
*/
#define ETH_DIRECT_FORWARD_ENABLE (STD_OFF)
/**
* @brief
*/
#define MAX_RING_SIZE_POWER (3U)

/** \brief  Configuration: ETH_NO_CACHEABLE_NEEDED
- if STD_ON, Eth driver will not include dcache maintain code.
- if STD_OFF,Eth driver will include dcache maintain code.
*/
#define ETH_NO_CACHEABLE_NEEDED (STD_OFF)

/**
* @brief
*/
typedef enum  {
    PTP_V1=1,
    PTP_V2=2
} ptp_version_t;

typedef enum  {
    PTP_MASTER=0,
    PTP_SLAVE
} ptp_mode_t;

typedef enum  {
    ALL_RX_PACKET,
    ALL_RX_PTP_PACKET,
    SPECIFIC_RX_PTP_PACKET,
} ptp_rx_filter_t;

typedef enum  {
    ETH1ToETH2,
    ETH2ToETH1,
} drct_fwd_direction_t;

typedef enum  {
    ETH_TCP,
    ETH_UDP,
} port_filter_prot_t;

#define CTRL0_TX_BUFF_SIZE     9600U
#define CTRL0_TX_BUFF_COUNT    52U

#define CTRL0_RX_BUFF_SIZE       12800U
#define CTRL0_RX_BUFF_COUNT      8U

#define ETH_MAX_CORES   (5U)

typedef struct
{
    /* */
    uint16 FifoBufLenByte;
    uint16 FifoBufTotal;
    uint16 FifoIdx;
    /* */
    uint32 BufSize;
} Eth_CtrlConfigFifoType;
/* */
typedef Eth_CtrlConfigFifoType Eth_EgressFifoType;
/* */
typedef Eth_CtrlConfigFifoType Eth_IngressFifoType;
/* */
typedef struct {
    uint32 idleSlopeOrWeight;
    uint32 sendSlope;
    uint32 hiCredit;
    uint32 loCredit;
    uint32 MemSize;
    uint8  PriortyMin;
    uint8  PriortyMax;
}Eth_EgressQueueCBSType;

typedef struct
{
    /* instance  */
    const uint32  SocCtrlIdx;
    /* Rate */
    const uint32  MacLayerSpeed;
    /* MacLayerType */
    const uint32  MacLayerType;
    /* MacLayerSubType */
    const uint32 MacLayerSubType;
    /* */
    const Eth_IngressFifoType* IngressFifoConfig;
    /* */
    const Eth_EgressFifoType* EgressFifoConfig;
    /* Mtu*/
    const uint16  Mtu;
    /* Enable interrupt requests for frame reception event */
    const boolean EnableRxInterrupt;
    /* Enable interrupt requests forframe transmission event */
    const boolean EnableTxInterrupt;
    /* Support MDIO for current controller */
    const boolean MiiSupport;
    /* Enable rxc delay */
    const boolean EnableRxcDelay;
    /* Enable txc delay */
    const boolean EnableTxcDelay;
    /* Instance ID of the controller */
    const uint8  EthCtrlIdx;
    /* EgressFifo Number */
    const uint8 EgressFifoNumber;
    /* IngressFifo Number */
    const uint8 IngressFifoNumber;
    /* Mac address low 32 bit*/
    const uint32  MACAddrLow;
    /* Mac address high 32 bit*/
    const uint32  MACAddrHigh;
    /* Mac rx packet timestamp Snapshot   */
    const ptp_rx_filter_t rxfilter;
    /* ptp mode master/slave*/
    const ptp_mode_t  ptp_mode;
    /* ptp protocol version */
    const ptp_version_t ptp_version;
    /* TrafficShaper */
    const uint32 TrafficShaper;
    /* TxTrafficAlgorithms */
    const uint32 TxTrafficAlgorithms;
    /* mtl mem assigned policy */
    const uint32 MtlQueueMemPolicy;
    /* queue cbs/weight config array */
    const Eth_EgressQueueCBSType* CbsCfg;
} Eth_CntrlConfigType;


typedef struct
{
  /* Store address of controller configuration for the current core */
  const Eth_CntrlConfigType* EthCntrlConfigPtr;
  /* Store maximum controllers allocated to current core */
  const uint8          EthMaxControllers;
}Eth_CoreConfigType;

typedef struct
{
  /* Array to store starting addresses of Core Configuration */
  const Eth_CoreConfigType* EthCoreConfig[ETH_MAX_CORES];

}Eth_ConfigType;

extern CONST(Eth_ConfigType, ETH_CONST) Eth_Control_Config;

#ifdef __cplusplus
}
#endif
#endif /*ETH_CFG_H_*/
